The present invention relates to an improved semiconductor memory device, and more particularly to an improved method for driving bit lines of the memory device.
To operate a static semiconductor memory device (S-RAM) at a high speed, there has been proposed a method in which the amplitude of the varying voltage in bit lines is reduced in the readout mode of the memory device. In the memory device based on this method, load elements of bit lines, transfer gates of memory cells, and transistors to drive the memory cells are turned on in the read out mode. The voltage in the bit line through which data "0" is read out is set between power source voltage and ground voltage. Such a memory device is disclosed by O. Minato in his paper "A HIGH COMOS II8k.times.8b Static RAMs" of "1982 IEEE International Solid-state Conference, DIGEST OF TECHNICAL PAPERS", or in "A 256k CMOS SRAM Variable-Impedance Loads" of "1985 International Solid-State Conference, DIGEST OF TECHNICAL PAPERS". In this type of memory device, current (through-current) flows through a path between a power voltage application point and ground. The memory device has a number of columns. For this reason, in the read out mode, the current flows into bit lines in the unselected columns. When each memory section consists of 128 columns, and the number of addressable columns is 8, the through-current also flows through all of the remaining columns of 120. It is for this reason that the conventional memory device consumes a lot of current.
The constant need for faster data processing rates, and higher memory device package density, creates a need for faster RAMs.